1. Field of the Invention
The present invention relates to a semiconductor device having a thin film transistor (which will also be referred to merely as a "TFT") and a method of manufacturing the same. In particular, the present invention relates to a semiconductor device having a TFT which can prevent reduction of a channel length of the TFT and can reduce a contact resistance of a connection between the TFT and an interconnection layer, and also relates to a method of manufacturing the same.
2. Description of the Related Art
As is well known, a static random access memory (which will be referred to merely as an "SRAM" hereinafter) is a kind of a semiconductor device having a TFT. A structure of the conventional SRAM and a method of manufacturing the same will be described below with reference to FIGS. 61-74.
FIG. 61 is an equivalent circuit diagram showing an example of a memory cell of the conventional SRAM. Referring to FIG. 61, a memory cell 150 includes a CMOS flip-flop connected between a power supply Vcc and a ground Vss, bit lines 151 and 152, and NMOS field effect transistors Q5 and Q6 for access which are provided between the CMOS flip-flop and bit lines 151 and 152, respectively.
The flip-flop includes two cross-coupled CMOS inverters. One of the inverters is formed of a PMOS field effect transistor Q1 and an NMOS field effect transistor Q2. The other inverter is formed of a PMOS field effect transistor Q3 and an NMOS field effect transistor Q4. Gate electrodes of the transistors Q5 and Q6 are connected to a word line 153.
FIG. 62 is a plan showing an example of the conventional SRAM. FIG. 63 is a cross section taken along line A--A in FIG. 62. The sectional structure of the SRAM shown in FIG. 63 is disclosed, e.g., in IEEE Electron Device Letters, Vol. EDL-4, No. 8, 1983, pp 272-274 and Electronic Information Communication Institute Technology Research Report., Vol. 89, No. 67, 1989, pp 1-6.
Referring to FIGS. 62 and 63, a semiconductor substrate 101 is provided at its main surface with a p-well region 102. Element isolating oxide films 104 are formed in the surface of the p-well region 102. At the vicinity of the lower surface of each element isolating oxide film 104, there is formed a p-type impurity region 103 which functions as a channel stopper.
The p-well region 102 is provided at its surface with n-type low concentration impurity regions 107a and 107b with predetermined spaces therebetween. The p-well region 102 is also provided at its surface with n-type high concentration impurity regions 109a and 109b partially overlapping the n-type low concentration impurity regions 107a and 107b. The p-well region 102 is further provided at its surface with n-type impurity regions 110 and 120 which are located in contact portions between the n-type high concentration impurity regions 109b and interconnection layers located above the same for reducing a contact resistance.
On the surface of the p-well region 102, there are formed gate electrodes 106a and 106b with gate insulating films 105a and 105b therebetween. Side wall insulating films 108a and 108b are formed on side walls of the gate electrodes 106a and 106b, respectively. The n-type impurity region 110 is electrically connected to a drain region 116b of a TFT through a contact electrode 111a formed on the n-type impurity region 110.
The gate electrode 106a is covered with interlayer insulating films 112 (112a and 112b). An interconnection layer 111b which is electrically connected to the power supply Vcc is formed at a predetermined position on the interlayer insulating film 112a.
The contact electrode 111a and interconnection layer 111b contain n-type impurity introduced thereinto because they are connected to the n-type impurity region. A gate electrode 113 of the TFT is formed at a predetermined position on the interlayer insulating film 112b. The gate electrode 113 of the TFT is covered with a gate insulating film 113a. On the gate insulating film 113a, there are formed source/drain regions 116b and 116c of the TFT, between which a channel region 116a of the TFT is formed.
The source/drain regions 116b and 116c of the TFT and the channel region 116a of the TFT are formed in the same layer, e.g., made of polysilicon. The source/drain regions 116b and 116c of the TFT are electrically connected to the interconnection layer 111b and the contact electrode 111a, respectively.
The TFT and gate electrode 106b are covered with an interlayer insulating film 118, which is provided at a predetermined position with a contact hole 119. A barrier metal layer 121 is formed on the interlayer insulating film 118 and the inner surface of the contact hole 119. An aluminum interconnection layer 122 is formed on the barrier metal layer 121. A passivation film (P-SiN film) 123 is formed on the aluminum interconnection layer 122.
In the above structure, a pair of the n-type low concentration impurity regions 107a, a pair of the n-type high concentration impurity regions 109a, the gate insulating film 105a and the gate electrode 106a constitute the N-type MOS transistor. Also, a pair of the n-type low concentration impurity regions 107b, a pair of the n-type high concentration impurity regions 109b, the gate insulating film 105b and the gate electrode 106b constitute the N-type MOS transistor.
The gate electrode 113, gate insulating film 113a, source/drain regions 116b and 116c, and channel region 116a constitute the TFT.
Referring now to FIGS. 64-74, a method of manufacturing the conventional SRAM having the structure described above will be described below. FIGS. 64-74 are fragmentary cross sections showing first to eleventh steps of a process of manufacturing the conventional SRAM having the structure described above.
Referring to FIG. 64, the n-type semiconductor substrate 101 is first prepared. Referring to FIG. 65, the p-well region 102 is formed in the main surface of the semiconductor substrate 101. The element isolating oxide films 104 are formed at predetermined positions in the surface of the p-well region 102. The p-type impurity region 103 which functions as the channel stopper is formed at the vicinity of the lower surface of each element isolating oxide film 104. The gate insulating film 105 is formed on the surface of the p-well region 102.
Referring now to FIG. 66, a polysilicon layer 106 is formed on the gate insulating film 105 by the CVD method or the like. A resist pattern 130 is formed at predetermined positions on the polysilicon layer 106. Using the resist pattern 130 as a mask, the polysilicon layer 106 is etched to form the gate electrodes 106a and 106b, as shown in FIG. 67.
Using the gate electrodes 106a and 106b, n-type impurity is introduced into the main surface of the semiconductor substrate 101, whereby the n-type low concentration impurity regions 107a and 107b are formed. The side wall insulating films 108a and 108b are formed on the side walls of the gate electrodes 106a and 106b, respectively.
Using the gate electrodes 106a and 106 as well as side wall insulating films 108a and 108b as a mask, n-type impurity is introduced into the main surface of the semiconductor substrate 101, whereby the n-type high concentration impurity regions 109a and 109b are formed. Thereby, the adjacent two N-type MOS transistors are completed.
Referring to FIG. 68, the interlayer insulating film 112a is formed entirely on the main surface of the semiconductor substrate 101 by the CVD method or the like. A contact hole is formed at a portion of the interlayer insulating film 112a at which the n-type impurity region 110 is to be formed. n-type impurity is introduced into the main surface of the semiconductor substrate 101 through the contact hole to form the n-type impurity region 110. The contact electrode 111a which is electrically connected to the n-type impurity region 110 is formed on the n-type impurity region 110. Simultaneously with this, the interconnection layer 111b to be electrically connected to the power supply Vcc is formed at the predetermined position on the interlayer insulating film 112a.
Referring to FIG. 69, the interlayer insulating film 112b is formed on the interlayer insulating film 112a. The gate electrode 113 of the TFT is formed at the predetermined position on the interlayer insulating film 112b.
Referring to FIG. 70, the gate insulating film 113a is formed to cover the gate electrode 113. A contact hole 115a is formed in portions of the interlayer insulating film 112b and gate insulating film 113a located above the contact electrode 111a. Simultaneously, a contact hole 115b is formed in portions of the interlayer insulating film 112b and gate insulating film 113a located above the interconnection layer 111b.
Referring to FIG. 71, a polysilicon layer 116 is formed, which extends over the contact electrode 111a and interconnection layer 111b and has a portion located above the gate electrode 113 with the gate insulating film 113a therebetween. The polysilicon layer 116 contains n-type impurity introduced thereinto.
Referring to FIG. 72, a resist pattern 131 is formed on a region of the polysilicon layer 116 in which the channel region 116a is to be formed. Using the resist 131 as a mask, p-type impurity (e.g., BF.sub.2.sup.+) is implanted into the polysilicon layer 116 to form the source/drain regions 116b and 116c of the TFT. Thereafter, the resist pattern 131 is removed.
Referring to FIG. 73, the interlayer insulating film 118 is formed entirely on the main surface of the semiconductor substrate 101. The interlayer insulating film 118 is reflowed. The contact hole 119 is formed at a predetermined position in the interlayer insulating film 118. n-type impurity is introduced through the contact hole 119 into the main surface of the semiconductor substrate 101 to form the n-type impurity region 120.
Referring to FIG. 74, the barrier metal layer 121 is formed on the interlayer insulating film 118 and the inner surface of the contact hole 119. The aluminum interconnection layer 122 is formed on the barrier metal layer 121 by the sputtering method. The passivation film (P-SiN) 123 is formed on the aluminum interconnection layer 122. Through the steps described above, the conventional SRAM shown in FIG. 63 is completed.
The conventional SRAM described above, however, has following problems, which will be described below with reference to FIGS. 75-77, which are schematic diagrams showing the problems of the conventional SRAM.
Referring first to FIG. 75, a first problem of the conventional SRAM will be described below. Referring to FIG. 75, two interfaces 125a and 125b exist between the channel region 116a and the source/drain regions 116b and 116c immediately after the formation of the TFT. The interfaces 125a and 125b are spaced by a distance L as shown in FIG. 77. In other words, the TFT has a channel length of L.
However, the interlayer insulating film 118 is formed on this TFT, as shown in FIG. 63. The interlayer insulating film 118 is thermally treated for planarization. During this treatment, the p-type impurity introduced into the source/drain regions 116b and 116c diffuses into the channel region 116a.
As a result, two interfaces 126a and 126b are newly formed between the source/drain regions 116b and 116c and the channel region 116a. A distance L1 between the interfaces 126a and 126b is smaller than the distance L between the interfaces 125a and 125b. Thus, the channel length of the TFT is reduced.
Thereby, the source/drain withstanding voltage of the TFT decreases. This results in a problem that punchthrough is liable to occur in the TFT. If the degree of integration is further improved in the future, such a problem may arise that the channel region 116a may disappear due to the diffusion of impurity described above.
As a measure for overcoming the above problem, conditions for the heat treatment effected on the interlayer insulating film 118 may be modified, for example, by lowering the temperature of the heat treatment and/or reducing a time period for the same. This can suppress the degree of diffusion of the p-type impurity. However, the change of conditions for the heat treatment causes a problem that difference in level in the SRAM cannot be sufficiently reduced.
In order to avoid the above problem relating to reduction of the channel length of the TFT without modifying the conditions for heat treatment, the channel length itself of the TFT may be set in advance to be longer than the desired channel length. However, the channel of the TFT initially having the long length may disadvantageously affect the high integration.
Then, a second problem of the conventional SRAM will be described below with reference to FIGS. 76 and 63. This second problem is caused in a portion corresponding to a connection region H between the source region of the PMOS field effect transistor and the power supply Vcc in FIG. 61.
Referring to FIGS. 76 and 63, the source region 116b of the TFT is connected to the interconnection layer 111b, which is connected to the power supply Vcc and generally contains n-type impurity introduced thereinto.
Meanwhile, the source region 116b of the TFT contains p-type impurity introduced thereinto. Therefore, if the power supply Vcc, e.g., of 5 V is used, a positive potential (5 V) is applied at a connection portion between the source region 116b of the TFT and the interconnection layer 111b, and the interconnection layer 111b containing the n-type impurity introduced thereinto receives the same. Thus, reverse bias is applied to a pn junction portion formed between the source region 116b of the TFT and the interconnection layer 111b. Consequently, the junction portion has a large resistance. As a result, such a problem is caused that characteristics of SRAM, e.g., relating to an operation speed are adversely affected.
A third problem of the conventional SRAM will be described below with reference to FIGS. 77 and 63. The contact electrode 111a is electrically connected to the drain region 116c of the TFT as shown in FIGS. 77 and 63.
It is preferable, in general, that a thickness of the semiconductor layer in which the source/drain regions 116b and 116c and channel region 116a of the TFT are formed is thin by the following reason. As is well known, a leak current flows through the TFT during standby of SRAM (i.e., in a data holding state) even if the TFT is off.
In order to suppress the amount of leak current, several measures are employed such as reduction of a thickness of the semiconductor layer in which the channel region is formed. Thereby, a sectional area of the portion of the semiconductor layer forming the channel region can be small. As a result, the amount of leak current flowing through the channel region can be reduced.
By the above reason, it has been considered that, in the TFT, it is preferable to reduce the thickness of the semiconductor layer in which the channel region 116a and source/drain regions 116b and 116c are formed.
As described above, the following problem is caused by the reduction of thickness of the semiconductor layer including the source/drain regions 116b and 116c of the TFT.
Referring to FIG. 77 again, the p-type impurity is introduced into the source/drain regions 116b and 116c of the TFT, as described before. However, since the source/drain regions 116b and 116c of the TFT are formed in the thin layer, the p-type impurity such as BF.sub.2 is liable to be introduced into a portion, i.e., contact electrode 111a in this case, which is located under the drain region 116c during introduction of the p-type impurity. The same is true with respect to the junction portion between the source region 116b of the TFT and the interconnection layer 111b.
Simultaneously, the n-type impurity is introduced into the contact electrode 111a, as described before. Therefore, there is high possibility that an interface of pn junction is formed in the contact electrode 111a due to the fact that the p-type impurity penetrates the drain region of the TFT and is introduced into the contact electrode 111a.
If the polysilicon layer containing the n-type impurity introduced thereinto is in contact with the polysilicon layer containing the p-type impurity introduced thereinto, a smaller resistance is obtained in the case where the pn junction is formed at the interface (contact surface) between the two polysilicon layers, compared with the case where the pn junction is formed in one of the polysilicon layers. The is due to the fact that a substantial contact area of the contact surface between the two polysilicon layers is relatively small.
Therefore, the resistance becomes large due to the formation of an interface 124 of pn junction in the contact electrode 111a, compared with the case where the pn junction is formed at the interface between the contact electrode 111a and drain region 116c. This results in the problem that the performance of the TFT is adversely affected.